Conventionally, an arbitration circuit is known that arbitrates a conflict caused in a data transfer such as packet transfer processing in a computer system or a communication system. Hereinafter, this arbitration circuit is referred to as an “arbiter”.
Some technology for reducing the length of time required for a packet to pass through an arbiter has been developed. For example, such technology has been achieved by monitoring the latency time that elapses after a packet reaches a queue and by increasing the priority level of a packet that has waited for a long time, and thereby reducing the amount of time the packet stays at the queue as much as possible.
In relation to the above-mentioned technology, a communication control device is known that enables good real-time response and fast collision control over the network. This is achieved by increasing the priority of a packet whose number of collisions is equal to or larger than a preset value when the transmission of a packet has failed due to the collision of the packet on the network.
FIG. 12 is a diagram illustrating the related art in which arbiters are provided at multiple levels.
An arbiter 1201 of FIG. 12 compares a timer value of a timer 1202 that measures the latency time of a packet stored in a queue #0 with a timer value of a timer 1203 that measures the latency time of a packet stored in a queue #1. The arbiter 1201 then switches a selector 1204 so as to prioritize an output of the packet whose latency time is longer.
Subsequently, a packet stored in the queue #0 or queue #1 is stored in a queue #2 via the selector 1204.
The arbiter 1211 compares a timer value of a timer 1212 that measures the latency time of a packet stored in the queue #2 with a timer value of a timer 1213 that measures the latency time of a packet stored in the queue #3. The arbiter 1211 then switches a selector 1214 so as to prioritize an output of the packet whose latency time is longer.
Subsequently, a packet stored in the queue #2 or queue #3 is output via the selector 1214. Hereinafter, a circuit in which an arbiter is arranged at multiple levels as illustrated in FIG. 12 is referred to as “multilevel arbiter”.    Patent Document 1: Japanese Laid-open Patent Publication No. 63-278439